This application is related to Japanese application No. 2000-167644 filed on Jun. 5, 2000, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device. In particular, it relates to a process for manufacturing a semiconductor device comprising an interlayer insulating film in which fine connection holes are formed to have a great aspect ratio and to reach a lower wiring layer.
2. Description of Related Art
As semiconductor devices are designed to be further miniaturized and wirings are multiplied, higher accuracy is required for miniaturization processes such as dry etching. For example, when a connection hole such as a contact hole is formed by etching, a diameter of the connection hole formed in an interlayer insulating film becomes small and an aspect ratio is increased. As a result, microloading effect (the smaller the diameter becomes, the more the etching rate is reduced or the etching is stopped) remarkably occurs, which causes malformation of the contact hole.
Further, after a photolithography step, the ratio of an area of the connection hole to an area of a resist film on a silicon wafer is reduced. Accordingly, an amount of CF gas in etching plasma is relatively increased in order to perform etching to a satisfactory degree under this condition. Then, a deposit derived from the CF gas is largely generated at the bottom of the connection hole, which raises electrical resistance of the connection hole. For example, it is known that use of a mask in which the ratio of the connection hole area (the ratio of the connection hole area with respect to an area of one chip) is as high as about 7% reduces the electrical resistance more, i.e., the CF deposit is reduced, as compared with use of a mask in which the ratio of the connection hole area is as low as about 3%.
In order to eliminate an excess of the CF gas, there has been proposed a method of introducing a small amount of oxygen-containing gas such as O2 or CO into the plasma. However, in this method, O in the oxygen-containing gas and C in the resist film are reacted to form CO and then volatilized. This facilitates the reduction of the resist film and as a result, the connection hole is widened at the top thereof. This is problematic since an alignment margin (top borderless margin) is reduced. That is, if the connection hole is widened at the top thereof, short-circuit occurs between metal wiring layers (upper wiring layers) connected with the top portion of the connection hole. The connection hole and the wiring layer are generally designed to permit a certain degree of misalignment of them. However, as the semiconductor device is further miniaturized, the alignment margin for the photolithography step is reduced, which makes difficult to prevent the short-circuit. Misalignment between the wiring layers and the connection hole is referred to as xe2x80x9ctop borderlessxe2x80x9d.
Further, as disclosed in Japanese Unexamined Patent Publication No. Hei 7 (1995)-201994, there has also been proposed a method of forming a dummy connection hole in addition to the connection hole, utilizing an etch stop layer in the interlayer insulating film. According to this method, oxygen is released in an etching atmosphere when the dummy connection hole is etched, an excess of the CF gas is eliminated and the amount of the CF deposit is controlled. Thus, the connection hole can be formed with high uniformity and reproducibility.
In order to control the amount of the CF deposit and to form the well-configured connection hole excellent in electrical properties with good reproducibility as described above, the dummy connection hole is generally provided to supply oxygen. However, the method of Japanese Unexamined Patent Publication No. Hei 7 (1995)-201994 requires additional steps of depositing an etch stop layer, removing the etch stop layer from a region for forming the connection hole and depositing an interlayer insulating film, as compared with the usual introduction of the oxygen-containing gas. Further, when the dummy connection hole reaches the etch stop layer, the surface of the insulating film formed of SiO2 is not exposed so that the supply of oxygen for controlling the amount of the CF deposit is stopped. This is considered to increase the CF deposit at the bottom or the sidewalls of the connection hole. If the CF deposit is excessively generated at the bottom of the connection hole, defects of the semiconductor device such as increase in electrical resistance are resulted.
According to the present invention, provided is a process for manufacturing a semiconductor device having a lower wiring layer, an interlayer insulating film and an upper wiring layer in this order and a connection hole formed in the interlayer insulating film on the lower wiring layer, wherein the connection hole is provided by: forming a photoresist layer on the interlayer insulating film; and forming in the photoresist layer an opening for the connection hole which exposes the interlayer insulating film at the bottom thereof and an opening for a dummy connection hole which does not expose the interlayer insulating film at the bottom thereof.
In the present invention, a resist pattern as shown in FIG. 1(a) is formed to eliminate the steps of depositing an etch stop layer, removing the etch stop layer from a region for forming the connection hole and depositing an interlayer insulating film, which have been additionally performed in the method of Japanese Unexamined Patent Publication No. Hei 7 (1995)-201994, as well as washing steps and examining steps involved in these steps. Further, the present invention exhibits effects equivalent to those of the above-mentioned prior art by merely performing a photolithography step of forming the connection hole and a step of examining the thus formed connection hole. Moreover, since the dummy connection hole is formed without utilizing the etch stop layer, oxygen is supplied until the formation of the connection hole by etching is completed.
At the beginning of the etching, a resist layer exists at the bottom of the opening for the dummy connection hole. Therefore the amount of oxygen supplied by the interlayer insulating film is considered to be smaller than that in the method disclosed by Japanese Unexamined Patent Publication No. Hei 7 (1995)-201994. However, it is considered that the etching is not stopped since the aspect ratio of the connection hole is relatively small at the beginning of the etching. The oxygen is actually required when the aspect ratio of the connection hole is increased, namely, when the etching is finished. In the present invention, oxygen for controlling the amount of the CF deposit is sufficiently supplied at the time when the etching is completed.
When a gas capable of supplying oxygen such as O2 or CO is used as the etching gas in a general use amount, the effect caused by oxygen is excessive so that the etching rate of the interlayer insulating film with respect to the lower wiring layer or the resist layer is reduced. That is, the amount of oxygen required for controlling the amount of the CF deposit is very small so that it is extremely difficult to adjust the amount by feeding a large amount of carrier gas. In the present invention, however, a required amount of oxygen is effectively supplied.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.